The scaling of VLSI circuits is a constant effort. Smaller integrated circuits allow more devices to be formed in one semiconductor chip. Additionally, power consumption and performance are also improved. With circuits becoming smaller and faster, improvement in device driving current is becoming more important, which can be increased by improving carrier mobility. Among efforts made to enhance carrier mobility, forming a stressed channel region is a known practice. The performance of a MOS device can be enhanced through a stressed-surface channel. This technique allows performance to be improved at a constant gate length without adding complexity to circuit fabrication or design.
It has been well known that tensile stress can improve NMOS device performance and compressive stress can improve PMOS device performance. A commonly used method for applying stress to the channel region is to form a stressed contact etch stop layer (CESL) on a MOS device. The stressed CESL introduces a stress into the channel region. Therefore, the carrier mobility is improved. Typically, there are three factors affecting the stress that can be applied by the CESL. The first factor is the inherent stress in the CESL. Currently, inherent stresses are capped at about 2 GPa for tensile stresses and about −3 GPa for compressive stresses. The second factor is the thickness of the CESL. Thicker CESLs apply higher stresses to the channel regions. However, the thicknesses of the CESLs are limited by design rules and the critical dimension. The third factor is cutting effects, which are partially determined by how far away the CESL extends from the source/drain regions. The further the CESL extends, the smaller the cutting effects, and the greater the stresses that are applied.
Cutting effects may be caused by the formation of contact plugs. To form contact plugs, openings have to be formed in the CESLs, and thus the stresses applied by the CESLs are adversely affected. It has been found that a stress in a channel region is related to the distance between a central line of a gate electrode and the nearest edge of contact plugs. The greater the distance, the greater the stress that is applied. When the MOS devices become smaller, the distance becomes smaller, and the stress is reduced more. Such a problem is expected to worsen for future-generation integrated circuits. A semiconductor device that may overcome the previously discussed deficiencies of the prior art is thus needed.